The Gaudí Suite
The Gaudí Suite is an open-source hardware ecosystem inspired by Catalan Modernisme, spanning the full stack of digital design from a reusable RTL library (Trencadís-RTL) and a custom 32-bit RISC-V CPU (Vitrall) to a complete System-on-Chip targeted for both FPGA (La Pedrera) and ASIC (La Sagrada Familia) implementation.
About This Project
The goal of "The Gaudí Suite" was to master the complete, vertical process of modern hardware creation, from a single logic gate to a physical, custom-designed integrated circuit. The project rejects the idea of purely functional, sterile design by embracing a philosophy of "Electronic Modernism", where engineering is infused with the artistry, structural ingenuity, and narrative depth found in the works of Antoni Gaudí. This suite is not just a collection of hardware modules; it's an architectural system with a story.
The process began with laying the foundation: Trencadís-RTL, a library of reusable "mosaic pieces". This collection of SystemVerilog peripherals (GPIO, UART, SPI) and fundamental components (FIFOs, synchronizers) are all designed to be modular and robust, forming the building blocks for any system. The centerpiece of the architecture is the Vitrall core, a custom-designed 32-bit RISC-V CPU compliant with the RV32GB ISA. Like a stained-glass window, it's the artistic and logical heart of the system, transforming simple data into complex results.
These pieces are integrated into La Pedrera, a complete System-on-Chip and a magnificent, functional prototype implemented on an FPGA. This serves as the proof-of-concept for the entire architecture. The ultimate and most ambitious goal of the project is La Sagrada Familia: the physical realization of the SoC as an ASIC using open-source tools. This represents the permanent "magnum opus", a testament to the immense challenge and dedication required to create custom silicon.
One of the primary challenges was managing the immense complexity of this full-stack endeavor as a solo developer. To overcome this, I adopted a "strategic tooling" mindset. Instead of relying on slow, manual iteration, I focused on building custom tools to accelerate my workflow. A key example was developing a real-time control and telemetry GUI using the Web Serial API to tune a complex mechatronic system, reducing a month-long task to a matter of days. This philosophy of building better tools to build better systems is a core tenet of the project.
Technologies Used
- Hardware Description: SystemVerilog, RISC-V ISA
- Verification & CI/CD: Verilator, Yosys, GitHub Actions
- Bus Protocol: Wishbone
- ASIC Toolchain: The OpenROAD Project, Sky130 PDK
- Firmware Development: C, Assembly
- Documentation: Markdown, MkDocs, Python